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ISL55110, ISL55111
Data Sheet March 21, 2007 FN6228.1
Dual, High Speed MOSFET Driver
The ISL55110 and ISL55111 are dual high speed mosfet drivers intended for applications requiring accurate pulse generation and buffering. Target applications include Ultrasound, CCD Imaging, Automotive Piezoelectric distance sensing and clock generation circuits. With a wide output voltage range and low on resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew as required in large CCD array imaging applications. The ISL55110 and ISL55111 are compatible with 3.3V and 5V logic families and incorporate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. The ISL55110 has a pair of in-phase drivers while the ISL55111 has two drivers operating in antiphase. Both inputs of the device have independent inputs to allow external time phasing if required. The ISL55110 has a power down mode for low power consumption during equipment standby times, making it ideal for portable products. The ISL55110 and ISL55111 are available in 16 Ld Exposed pad QFN packaging and 8 Ld TSSOP. Both devices are specified for operation over the full -40C to +85C temperature range.
Features
* 5V to 12V Pulse Magnitude * High Current Drive 3.5A * 6ns Minimum Pulse Width * 1.5ns Rise and Fall Times, 100pF Load Time * Low Skew * 3.3V and 5V Logic Compatible * In-Phase and Anti-Phase Outputs * Small QFN and TSSOP Packaging * Low Quiescent Current * Pb-free Plus Anneal Available (RoHS compliant)
Applications
* Ultrasound Mosfet Driver * CCD Array Horizontal Driver * Automotive Piezo Driver Applications * Clock Driver Circuits
Ordering Information
PART NUMBER ISL55110IRZ* (Note) ISL55110IVZ* (Note) ISL55111IRZ* (Note) ISL55111IVZ* (Note) PART TEMP. MARKING RANGE (C) PACKAGE 55 110IRZ 55110 IVZ -40 to +85 -40 to +85 16 Ld QFN (Pb-free) PKG. DWG. # L16.4x4A
Functional Block Diagram
ISLl55110 and ISL55111 DUAL DRIVER o VDD
8 Ld TSSOP M8.173 (Pb-free) 16 Ld QFN (Pb-free) L16.4x4A
VH
o
55 11IRZ 55111 IVZ
-40 to +85 -40 to +85
o
IN-A
OA
o
8 Ld TSSOP M8.173 (Pb-free)
*Add "-T" suffix for tape and reel.
o HIZ-QFN*
o
IN-B *
OB
o
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
GND o POWER DOWN
o
* HIZ AVAILABLE IN QFN PACKAGE ONLY * ISL55111 IN-B IS INVERTING
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL55110, ISL55111 Pinout
ISL55110 (16 LD QFN) TOP VIEW
NC NC NC NC
ISL55111 (16 LD QFN) TOP VIEW
NC NC
16 VDD ENABLE PD IN-B 1 2 3 4 5 IN-A
15
14
13 12 OB 11 GND 10 VH 9 OA VDD ENABLE PD IN-B 1 2 3 4
16
15
14
NC
13 12 OB 11 GND 10 VH 9 OA 8
6 NC
7 NC
8 NC
5 IN-A
6 NC
NC 7 NC
ISL55110 (8 LD TSSOP) TOP VIEW
VDD PD IN-B IN-A 1 2 3 4 8 OB 7 GND 6 VH 5 OA VDD PD IN-B IN-A 1 2 3 4
ISL55111 (8 LD TSSOP) TOP VIEW
8 OB 7 GND 6 VH 5 OA
Pin Descriptions
PIN VDD VH GND PD ENABLE IN-A IN-B, INB OA OB Logic Power. Driver High Rail Supply Ground, return for both VH rail and VDD Logic Supply. Power Down. Active Logic High places part in Power Down Mode. QFN Packages only. Provides high speed logic HIZ control of driver outputs while leaving device logic power on. Logic level input that drives OA to VH Rail or Ground. Not Inverted. Logic level input that drive OB to VH Rail or Ground. Not inverted on ISL55110, Inverted on ISL55111. Driver output related to IN-A. Driver output related to IN-B. FUNCTION
2
NC
FN6228.1 March 21, 2007
ISL55110, ISL55111
Absolute Maximum Ratings (TA = +25C)
VH+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VIN_A, VIN_V, PDN, ENABLE. . . . . . . . (GND-0.5V) to (VDD+0.5V) OA, OB. . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND-0.5) to (VH+0.5V) Maximum Peak Output Current . . . . . . . . . . . . . . . . . . . . . . (300mA) ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3KV
Thermal Information
Thermal Resistance JA (C/W) 16 Ld (4x4) QFN Package (Note 2) . . . . . . . . . . . . . 45 8 Ld TSSOP Package (Note 1) . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Recommended Operating Conditions
PARAMETER VH VDD TA TJ DESCRIPTION Driver Supply Voltage Logic Supply Voltage Ambient Temperature Junction Temperature VH = +12V, VDD = 2.7V to 5.5V, TA = +25C, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS CONDITIONS MIN 5 2.7 -40 TYP 12 MAX 13.2 5.5 +85 +150 UNIT V V C C
DC Electrical Specifications
PARAMETER LOGIC CHARACTERISTICS VIX_LH VIX_HL VHYS VIH VIL VIH VIL IIX_H IIX_L II_H II_L II_H II_L
Logic Input Threshold - Low to High Logic Input Threshold - High to Low Logic Input Hysteresis Logic Input High Threshold Logic Input Low Threshold Logic Input High Threshold Logic Input Low Threshold Input Current Logic High Input Current Logic Low Input Current Logic High Input Current Logic Low Input Current Logic High Input Current Logic Low
lIH = 1A: VIN_A, VIN_B lIL = 1A: VIN_A, VIN_B VIN_A,VIN_B PDN PDN ENABLE - QFN only ENABLE - QFN only VIN_A,VIN_B = VDD VIN_A, VIN_B = 0V PDN = VDD PDN = 0V ENABLE = VDD - QFN only ENABLE = 0V - QFN only
1.32 1.12
1.42 1.22 0.2
1.52 1.32
V V V
2.0 0 2.0 0 10 10 10 10
VDD 0.8 VDD 0.8 20 20 20 15 12
V V V V nA nA nA nA mA nA
-25
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FN6228.1 March 21, 2007
ISL55110, ISL55111
DC Electrical Specifications
PARAMETER DRIVER CHARACTERISTICS RDS IDC IAC VOH to VOL SUPPLY CURRENTS IDD IDD-PDN IH IH_PDN Logic Supply Quiescent Current Logic Supply Power Down Current Driver Supply Quiescent Current Driver Supply Power Down Current PDN = Low PDN = High PDN = Low, No resistive load DOUT PDN = High 4.0 6.0 12 15 1 mA A A A Driver Output Resistance Driver Output DC current (>2s) Peak Output Current Driver Output Swing Range Design Intent verified via simulation. VH voltage to Ground 3 OA, OB 3 100 3.5 13.2 6 mA A V (Continued)VH = +12V, VDD = 2.7V to 5.5V, TA = +25C, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
AC Electrical Specifications
PARAMETER SWITCHING CHARACTERISTICS tR,tF
VH = +12V, VDD = +3.6, TA = +25C, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
Driver Rise/Fall Time
OA,OB: CL = No Load 10% to 90%, VOH-VOL = 12V 10% to 90%, VOH-VOL = 10V OA, OB CL = 1nF 10% to 90%, VOH-VOL = 12V Figure 2, Load 100pF/1k
1.0 1.0 6.7 12.0 9.3
ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns
tR,tF
tpdR
Driver Rise/Fall Time Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay Input to Output Propagation Delay
tpdF tpdR tpdF tpdR tpdF tpdR tpdF tSkewR tSkewF FMAX TMIN PDEN* PDDIS* TEN* TDIS*
Figure 2, Load 220pF
12.5 10.2
Figure 2, Load 330pF
12.9 10.6
Figure 2, Load 680pF
14.1 12.1 <0.5 <0.5 70 6 0.7 1.4 0.3 1.4 1.0 1.6 0.7 1.6
Channel to Channel tpdR Spread with same Figure 2, All Loads loads both Channels Channel to Channel tpdF Spread with same Figure 2, All Loads loads both channels. Maximum Operating Frequency Minimum Pulse Width Power-down to Power-on Time Power-on to Power-down Time ENABLE to ENABLE Time (HIZ Off) ENABLE to ENABLE TIme (HIZ On)
ms ms ms ms
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FN6228.1 March 21, 2007
ISL55110, ISL55111
VH = 12V
+3V + 4.7F INPUT 0.1F
INX INPUT ISL55110 INPUT RISE AND FALL TIMES 2ns IN CL OUTPUT
0.4V
tr 90% OUTPUT 0V 10% 10% 90% tf
12V
FIGURE 1. TEST CIRCUIT RISE (TR)/FALL(TF) THRESHOLDS
VH = 12V
+3V + 4.7F INPUT 0.1F 50%
50%
IN-X INPUT ISL55110 INPUT RISE AND FALL TIMES 2ns IN CL OUTPUT
0.4V
tpdR 12V 50% 50% tpdF
OUTPUT OA AND OB ISLS55110 OUTPUT OA ISLS55111 0V
12V
OUTPUT OB ISLS55111 50% 0V tSKEWR = tpdR CHN1 - tpdR CHN2 50%
FIGURE 2. TEST CIRCUIT PROPAGATION TPD DELAY
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves
7.0 6.3 5.6 4.9 4.2 RON RON 3.5 2.8 2.1 1.4 0.7 0.0 3 4 5 6 7 8 9 10 VH, DRIVE RAIL (V) -40C 11 12 13 +85C +25C VDD 3.6V -50mA
(See Typical Performance Curves Discussion)
7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 3 4 5 6 7 8 9 10 VH, DRIVE RAIL (V) -40C 11 12 13 +85C +25C VDD 3.6V +50mA
FIGURE 3. DRIVER RON vs VH SOURCE RESISTANCE
FIGURE 4. DRIVER RON vs VH SINK RESISTANCE
4.00 50mA 3.66
4.00 50mA 3.66
RON ()
VH 5.0V 2.66 VH 12.0V
RON ()
3.33
3.33
2.66 VH 5.0V VH 12.0V
2.33
2.33
2.00 2.5
3.5 VDD (V)
4.5
5.5
2.00 2.5
3.5 VDD (V)
4.5
5.5
FIGURE 5. RON vs VDD SOURCE RESISTANCE
FIGURE 6. RON vs VDD SINK RESISTANCE
4.0
10 9 VDD 3.6V
3.8
8 7
IDD (mA)
IDD (mA) VH 5V AND 12V 3.5 VDD (V) 4.5 5.5
3.6
6 5 4 3
3.4
3.2
2 1 0 4 8 VH, DRIVE RAIL (V) 12
3.0 2.5
FIGURE 7. IDD vs VDD QUIESCENT CURRENT
FIGURE 8. IDD vs VH @ 50MHz (NO LOAD)
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
100 90 80 70 IH (mA) IH (A) 60 50 40 30 20 10 0 4 8 VH, DRIVE RAIL (V) 12 VDD 3.6V 200 180 160 140 120 100 80 60 40 20 0 4 8 VH, DRIVE RAIL (V) 12 VDD 3.6V
FIGURE 9. QUIESCENT IH vs VH
FIGURE 10. IH vs VH @ 50MHz (NO LOAD)
15.0 13.5 12.0 10.5 IDD (mA) IH (mA) 9.00 7.50 6.00 4.50 2.00 0.50 0.00 50M 66M VH 5.0V VDD 3.6V 100M 124M TOGGLE FREQUENCY IN Hz 128M
200 180 160 140 120 100 80 60 40 20 0 50M 66M 100M 124M TOGGLE FREQUENCY IN Hz 128M VH 5.0V VDD 3.6V
FIGURE 11. IDD vs FREQUENCY (DUAL CHANNEL, NO LOAD)L
FIGURE 12. IH vs FREQUENCY (DUAL CHANNEL, NO LOAD)
1.5
1.5
1.4 -40C LOGIC (V) 1.3 LOGIC (V) +85C
1.4 -40C
1.3
1.2
1.2
1.1
1.1 +85C
1.0 2.5
3.5 VDD (V)
4.5
5.5
1.0 2.5
3.5 VDD (V)
4.5
5.5
FIGURE 13. VIH LOGIC THRESHOLDS
FIGURE 14. VIL LOGIC THRESHOLDS
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
10 9 8 RISE TIME (ns) 7 6 5 4 3 2 1 0 -40 -10 +20 PACKAGE TEMP (C) +50
VH 12.0V VDD 3.6V
10 9 100pF/1k 330pF 680pF 1000pF FALL TIME (ns) 8 7 6 5 4 3 2 1 0 -40 -10 +20 PACKAGE TEMP (C) +50 +85
VH 12.0V VDD 3.6V
100pF/1k
330pF
680pF
1000pF
+ 85
FIGURE 15. tr vs TEMPERATURE
FIGURE 16. tf vs TEMPERATURE
20 18 PROPAGATION DELAY (ns) 16 14 12 10 8 6 4 2 0 -40 -10 +20 PACKAGE TEMP (C) +50
VH 12.0V VDD 3.6V
20 680pF 1000pF PROPAGATION DELAY (ns) 18 16 14 12 10 8 6 4 100pF/1k 2 0 -40 -10 +20 PACKAGE TEMP (C) +50
VH 12.0V VDD 3.6V
680pF
1000pF
330pF 100pF/1k
330pF
+85
+85
FIGURE 17. tpdr vs TEMPERATURE
FIGURE 18. tpdf vs TEMPERATURE
10 9 8 RISE TIME (ns) 7 6 5 4 3 2 1 0 2.5 3.5 VDD (V) 4.5 5.5 100pF/1k 330pF 680pF VH 12.0V 1000pF FALL TIME (ns)
10 9 8 7 6 5 4 3 2 1 0 2.5 VH 12.0V 3.5 VDD (V) 4.5 5.5 100pF/1k 330pF 680pF 1000pF
FIGURE 19. tr vs VDD
FIGURE 20. tf vs VDD
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
12.0 10.8 9.6 RISE TIME (ns) FALL TIME (ns) 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 VDD 3.3V 3 6 VH (V) 9 12 100pF/1k 330pF 680pF 1000pF 12.0 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 VDD 3.3V 3 6 VDD (V) 9 12 100pF/1k 330pF 680pF 1000pF
FIGURE 21. tr vs VH
FIGURE 22. tf vs VH
20 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 18 16 14 12 10 8 6 4 2 0 2.5 100pF/1k 3.5 VDD (V) 330pF 680pF 4.5 1000pF 5.5 VH 12.0V
20 18 16 14 12 10 8 6 4 2 0 2.5 100pF/1k 3.5 VDD (V) 330pF 680pF 4.5 1000pF 5.5 VH 12.0V
FIGURE 23. tpdr vs VDD
FIGURE 24. tpdf vs VDD
20 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 18 16 14 12 10 8 6 4 2 0 3 6 VH (V) 9 12 100pF/1k 330pF 680pF 1000pF VDD 3.3V
20 18 16 14 12 10 8 6 4 2 0 3 6 VH (V) 9 12 100pF/1k 330pF 680pF 1000pF VDD 3.3V
FIGURE 25. tpdr vs VH
FIGURE 26. tpdf vs VH
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
1.0 0.9 0.8 0.7 tskewF (ns) tskewR (ns) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 PACKAGE TEMP (C) +50 +85 680pF 330pF
VH 12.0V VDD 3.6V
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 PACKAGE TEMP (C) +50 +85 680pF AND 330pF
VH 12.0V VDD 3.6V
FIGURE 27. tskewr vs TEMPERATURE
FIGURE 28. tskewf vs TEMPERATURE
1.0 VH 12.0V 0.9 0.8 0.7 SKEW (ns) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 330pF 3.5 VDD (V) 4.5 5.5 680pF SKEW (ns)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 330pF 3.5 VDD (V) 4.5 5.5 680pF VH 12.0V
FIGURE 29. tskewr vs VDD
FIGURE 30. tskewf vs VDD
1.0 0.9 0.8 0.7 SKEW (ns) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3 330pF 6 VDD (V) 9 680pF
VDD 3.3V
1.0 0.9 0.8 0.7 SKEW (ns) 0.6 0.5 0.4 0.3 0.2 0.1 330pF 3 6 VDD (V) 9 12 680pF VDD 3.3V
12
0.0
FIGURE 31. tskewr vs VH
FIGURE 32. tskewf vs VH
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Typical Performance Curves Discussion
RON
RON Source tested by placing device in Constant Drive High Condition and connecting -50mA constant current source to the Driver Output. Voltage Drop measured from VH to Driver Output for RON calculations. RON Sink tested by placing device in Constant Driver Low Condition and connecting a +50mA constant current source. Voltage Drop from Driver Out to Ground measured for RON Calculations.
Pin Skew
Pin Skew measurements are based on the difference in propagation delay of the two channels. Measurements are made on each channel from the 50% point on the stimulus point to the 50% point on the driver output. The difference in the propagation delay for Channel A and Channel B is considered to be Skew. Both Rising Propagation Delay and Falling Propagation Delay are measured and reports as tSkewR and tSkewF.
50MHz Tests
50MHz Tests reported as No Load actually include Evaluation board parasitics and a single TEK 6545 fet probe. However no driver load components are installed, C6 through C9 and R3 through R6 are not populated.
Dynamic Tests
All dynamic tests are conducted with ISL55110, ISL55111 Evaluation Board(s). Driver Loads are soldered to the Evaluation board. Measurements are collected with P6245 Active Fet Probes and TDS5104 Oscilloscope. Pulse Stimulus is provided by HP8131 pulse generator. The ISL55110, ISL55111 Evaluation Boards provide Test Point Fields for leadless connection to either an Active Fet Probe or Differential probe. TP-IN fields are used for monitoring pulse input stimulus. TP-OA/B monitor Driver Output waveforms. C6 and C7 are the usual placement for Driver loads. R3 and R4 are not populated and provided for User-Specified, more complex load characterization.
General
Most dynamic measurements are presented in three ways. First over temperature with a VDD of 3.6V and VH of 12.0V. Second, at ambient with VH set to 12V and VDD data points of 2.5V, 3.5V, 4.5V and 5.50V. Third, the ambient tests are repeated with VDD of 3.3V and VH data points of 3V, 6V, 9V and 12V.
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Detailed Description
The ISL55110 and ISL55111 are Dual High Speed Mosfet Drivers intended for applications requiring accurate pulse generation and buffering. Target applications include Ultrasound, CCD Imaging, Automotive Piezoelectric distance sensing and clock generation circuits. With a wide output voltage range and low On Resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew as required in large CCD array imaging applications. The ISL55110 and ISL55111 are compatible with 3.3V and 5V logic families and incorporate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. The ISL55110 has a pair of in-phase drivers while the ISL55111 two drivers operating in antiphase. Both inputs of the device have independent inputs to allow external time phasing if required. In addition to power MOS drivers, the ISL55110, ISL55111 is well suited for other applications such as bus, control signal, and clock drivers on large memory of microprocessor boards, where the load capacitance is large and low propagation delays are required. Other potential applications include peripheral power drivers and charge-pump voltage inverters. rise and fall times. Use a ground plane if possible, or use separate ground returns for the input and output circuits. To minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the ISL55110, ISL55111 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A parallel combination of capacitors that has a low impedance over a wide frequency range should be used. A 4.7F tantalum capacitor in parallel with a low inductance 0.1F capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast rise or fall times. Such ringing will be aggravated by long inductive lines with capacitive loads. Techniques to reduce ringing include: 1. Reduce inductance by making printed circuit board traces as short as possible. 2. Reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. 3. Use small damping resistor in series with the output of the ISL55110, ISL55111. Although this reduces ringing, it will also slightly increase the rise and fall times. 4. Use good by passing techniques to prevent supply voltage ringing.
Input Stage
The input stage is a high impedance input with rise/fall hysteresis. This means that the inputs will be directly compatible with both TTL and lower voltage logic over the entire VDD range. The user should treat the inputs as high speed pins and keep rise and fall times to <2ns.
Power Dissipation Calculation
The Power dissipation equation has three components: Quiescent Power Dissipation, Power dissipation due to Internal Parasitics and Power Dissipation because of the Load Capacitor. Power dissipation due to internal parasitics is usually the most difficult to accurately quantitize. This is primarily due to Crow-Bar current which is a product of both the high and low drivers conducting effectively at the same time during driver transitions. Design goals always target the minimum time for this condition to exist. Given that how often this occurs is a product of frequency, Crowbar effects can be characterized as internal capacitance. Lab tests are conducted with Driver Outputs disconnected from any load. With design verification packaging, bond wires are removed to aid in the characterization process. Base on laboratory tests and simulation correlation of those results, the following equation defines the ISL55110, ISL55111 Power Dissipation per channel: P = VDD*3.3e-3 + 10pF*VDD^2*f + 135pF*VH^2*f + CL*VH^2*f (Watts/Channel)
Output Stage
The ISL55110, ISL55111 output is a high-power CMOS driver, swinging between ground and VH. At VH = 12V, the output impedance of the inverter is typically 3.0. The high peak current capability of the ISL55110, ISL55111 enables it to drive a 330pF load to 12V with a rise time of <3.0ns over the full temperature range. The output swing of the ISL55110, ISL55111 comes within < 30mV of the VH and Ground rails.
Application Notes
Although the ISL55110, ISL55111 is simply a dual levelshifting driver, there are several areas to which careful attention must be paid.
Grounding
Since the input and the high current output current paths both include the ground pin, it is very important to minimize and common impedance in the ground return. Since the ISL55111 has one inverting input, any common impedance will generate negative feedback, and may degrade the delay,
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FN6228.1 March 21, 2007
ISL55110, ISL55111
Where: 1. 3.3mA is the quiescent Current from the VDD. This forms a small portion of the total calculation. When figuring two channel power consumption, only include this current once. 2. 10pF is the approximate parasitic Capacitor (Inverters, etc.), which the VDD drives 3. 135pF is the approximate parasitic at the DOUT and its Buffers. This includes the effect of the Crow-bar Current. 4. CL is the Load capacitor being driven The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads. Power also depends on number of channels changing state and frequency of operation. The extent of continuous active pulse generation will greatly effect dissipation requirements. The user should evaluate various heat sink/cooling options in order to control the ambient temperature part of the equation. This is especially true if the user's applications require continuous, high speed operation. A review of the Theta-j ratings of the TSSOP and QFN package clearly show the QFN package to have better thermal characteristics. The reader is cautioned against assuming a calculated level of thermal performance in actual applications. A careful inspection of conditions in your application should be conducted. Great care must be taken to ensure Die Temperature does not exceed 150C Absolute Maximum Thermal Limits. Important Note: The ISL55110, ISL55111 QFN package metal plane is used for heat sinking of the device. It is electrically connected to the negative supply potential ground.
Power Dissipation Discussion
Specifying continuous pulse rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation / cooling necessities. Driver Output patterns also impact these needs. The faster the pin activity, the greater the need to supply current and remove heat. As detailed in the Power Dissipation Calculation Section, Power Dissipation of the device is calculated by taking the DC current of the VDD (logic) and VH Current (Driver rail) times the respective voltages and adding the product of both calculations. The average DC current measurements of IDD and IH should be done while running the device with the planned VDD and VH levels and driving the required pulse activity of both channels at the desired operating frequency and driver loads. Therefore the user must address power dissipation relative to the planned operating conditions. Even with a device mounted per Note 1 or 2 under Thermal Information, given the high speed pulse rate and amplitude capability of the ISL55110, ISL55111, it is possible to exceed the +150C "absolute-maximum junction temperature". Therefore, it is important to calculate the maximum junction temperature for the application to determine if operating conditions need to be modified for the device to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
Power Supply Sequencing
The ISL55110, ISL55111 references both VDD and the VH driver supplies with respect to Ground. Therefore apply VDD, then VH. Digital Inputs should never be open. Do not apply slow analog ramps to the inputs. Again place decoupling as close to the package as possible for both VDD and especially VH.
Special Loading
With most applications the user will usually have a special load requirement. Please contact Intersil for Evaluation Boards or to request a device characterization to your requirements in our lab.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.30 2.30 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.40 4.00 BSC 3.75 BSC 2.40 0.50 BSC 0.40 16 4 4 0.60 12 0.50 0.15 2.55 2.55 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 3/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN6228.1 March 21, 2007
ISL55110, ISL55111 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.116 0.169 0.246 0.0177 8 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.120 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 2.95 4.30 6.25 0.45 8 8o MAX 1.20 0.15 1.05 0.30 0.20 3.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 12/00
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6228.1 March 21, 2007

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